1. Field of the Invention
The present invention relates to an internal voltage generation circuit, and in particular to an internal voltage generation circuit which makes it possible to decreasing a power consumption of a semiconductor device by controlling an internal voltage generation circuit in accordance with an operation state and operation parameter of a semiconductor device.
2. Description of the Background Art
As shown in FIG. 1, a conventional internal voltage generation circuit includes a state decoder 10 for generating state signals STB, ACT and SUS which indicate an operation state of a semiconductor device, a controller 20 for generating driving signals VINTA and VINTS using the state signals STB, ACT and SUS of the state decoder 10, and an internal voltage generation unit 30 for generating internal voltages Vint, Vpp and Vbb using an output of the controller 20 and an external power voltage Vext.
The internal voltage generator 30 includes a drop voltage generation unit 31 for generating a drop voltage Vint used for driving an internal circuit from the external power voltage, a boosting voltage generation unit 32 for generating a booting voltage Vpp used for driving an internal circuit from the external power voltage Vext, and a sub-voltage generation unit 33 for generating a sub-voltage Vbb used for a substrate bias of an internal circuit from the external power voltage Vext.
The generation units 31, 32 and 33 of the internal voltage generation unit 30 are each formed of a standby mode voltage driving unit having a small driving capability and an active mode voltage driving unit having a large driving capability.
FIG. 2 illustrates a detailed circuit of the drop voltage generation unit 31. As shown therein, the drop voltage generation unit 31 includes a reference voltage generation unit REFC for generating a reference voltage VREF, an active mode voltage driving unit 31A which operates in the active mode, and a standby mode voltage driving unit 31S which operates in the standby mode and clock suspending mode. Here, the active mode voltage driving unit 31A includes an active mode voltage dividing unit DIVA formed of serially connected active mode first and second resistors RA1 and RA2, an active mode differential amplifier AMPA driven by an active mode drop voltage driving signal VINTA generated based on the outputs of the state decoder 10 and the controller 20 for comparing the reference voltage VREF with a voltage divided by the voltage dividing unit DIVA, and an active mode PMOS transistor PMA having its source receiving an external voltage Vext, its drain connected with the voltage dividing unit DIVA, and its gate receiving an output of the differential amplifier AMPA. A drop voltage Vint is outputted at a commonly connected node of the voltage dividing unit DIVA and the drain of the active mode PMOS transistor PMA.
In addition, the standby mode voltage driving unit 31S includes a standby mode voltage driving unit DIVS formed of serially connected standby mode first and second resistors RS1 and RS2, a standby mode differential amplifier AMPS driven by a standby mode drop voltage driving signal VINTS based on the outputs of the state decoder 10 and the controller 20 for comparing the reference voltage VREF with the voltage divided by the voltage dividing unit DIVS, and a standby mode PMOS transistor PMS having its source receiving an external voltage Vext, its drain connected with the voltage dividing unit DIVS, and its gate receiving an output of the differential amplifier AMPS. A drop voltage Vint is outputted at the commonly connected node of the voltage dividing unit DIVS and the standby mode transistor PMS.
The operation of the conventional internal voltage generation circuit will be explained.
First, the state decoder 10 detects an operation state and outputs the state signals STB, ACT and SUS of the standby mode, active mode, and clock suspending modes. In order to control the operation of the internal voltage generation circuit, the internal voltage generation unit 30 is independently provided for the standby mode voltage generation unit and the active mode voltage generation unit in accordance with the operation state of the device, so that it is possible to effectively control the current used for the internal voltage generation circuit.
Namely, since a small amount of the current is used for the circuit which uses the internal voltage in the standby mode or the clock suspending mode, even when the driving capability of the internal voltage generation circuit and the level detection sensitivity are low, a certain problem does not occur. When the standby mode voltage generation unit which has a small consumption of the current is used, and in the active mode, the active mode voltage generation unit which has a high driving capability of the internal voltage generation circuit and a high level sensitivity.
However, in the conventional internal voltage generation circuit, since the internal voltage generation circuit is controlled only using the state(active, standby, and clock modes) of the semiconductor device, the current consumption variables are not considered except for the state modes. Therefore, it is impossible to effectively decrease the consumption of the current.